Bitstorm · the detail

One product,
both halves.

Everything below is Bitstorm: the simulation engines, the debug that follows a run, the decoding of what the signals carried, and the measurements behind the claims. Start at the overview if you want the short version.

Simulation engines Debug and decode

Simulation engines

Verilator, ModelSim and Questa run a design on CPU cores. Bitstorm runs it on an NVIDIA GPU as well: thousands of GPU threads take the work that runs in parallel, and a fast CPU core takes the serial part — both on one simulation.

GPU ENGINE

Parallel work on thousands of threads

Datapaths, video pipelines and other wide, parallel logic go to the GPU. A CPU core runs the serial part and the testbench, in the same simulation.

COMPILED CPU

Serial designs as compiled code

Designs that are mostly sequential run as compiled code on CPU cores, multithreaded, and gain from each thread you give them.

EVENT MODE

Sources, four-state, timed

Runs designs and testbenches from their sources with four-state values, delays, delta cycles and SDF timing — the semantics a UVM testbench expects.

From RTL to one simulation

Compile

SystemVerilog, Verilog, VHDL and testbenches.

Analyze

Find the parallel and the serial work.

Partition

Split work between GPU threads and CPU cores.

Schedule

Order GPU and CPU work to run together.

Execute

Hybrid CPU and GPU engines, one simulation.

Results

run.json, log, and FST or VCD waves.

What it covers

LANGUAGES

SystemVerilog, Verilog, VHDL

SystemVerilog (IEEE 1800-2023, including Verilog 1364-2005), VHDL designs (IEEE 1076-2019), and the two mixed in one design.

VERIFICATION

UVM and constrained random

UVM 1.2 and 2020.3.1 in event mode, classes and constraints, functional coverage with merge and reports, SVA and PSL, plus SDF back-annotation.

INTEGRATION

DPI-C, VPI, VHPI, cocotb

DPI-C for C models; VPI and VHPI with cocotb in event mode; Xilinx's Vivado libraries in Verilog and VHDL with the 7 series SERDES; IEEE 1735 encrypted IP.

PLATFORMS

Windows for the GPU, Linux too

GPU engine: Windows 10 or 11 with an NVIDIA Ampere or newer GPU. CPU engines and event mode also run on Linux (Ubuntu 22.04 or later).

Debug and decode

Waves alone tell you a value changed. Bitstorm tells you what the value meant.

RUST-NATIVE

Native windows, portable core

A Rust workbench with native windows and a portable analysis core, so the same engine serves the GUI, scripts and agents.

GPU-RENDERED

Waves and hierarchy on the GPU

Browse waves and RTL with native GPU rendering. Background workers fetch values while you pan, zoom and open views.

AXI4-STREAM

Accepted transfers

Parse signals as an AXI4-Stream bus, with the transfers your design actually accepted.

VIDEO

Lines, frames, pixels

A UG934 video dissector on top of AXI4-Stream recovers lines and full-resolution images; inspect individual pixels and colours.

MEMORY

Sparse memory from writes

An AXI4-Lite dissector reconstructs memory from observed writes. Bytes nobody observed stay marked as unknown.

H.264

NAL units and slices

Feed a reconstructed output buffer into an H.264 dissector to read sequence headers and slices beside the hex dump.

Each decoded record links back to the bus transfers that supplied it, so a broken frame or a colour error traces to a specific transfer.

Large traces, fast queries

3–30 µspoint queries, warm p95

2–3 msdisplay queries, warm p95

20 GiBdisk-backed stress case

Indexed VCD and FST: exact values read from disk, with a bounded page cache instead of the whole trace in RAM.
Zoom from a full capture to a single transfer, compare signal values, and open extra views without waiting for a full load.
During a live run, new waveform data appears in place: set a time range before the run and watch it fill.

Query timings measured on a five-frame, 23-signal trace with default caches, on Windows and Linux, 14 October 2026. These are data-query times, not file-load times or frame rates. The 20 GiB case is a separate synthetic trace tested with a 32 MiB source-page cache.

Agent-ready

Simulate, measure and replay from the desktop, a script, or an AI tool — one shared session, one command set.

JSON

The simulator is drivable

Compile, run, pause, examine, force a value and collect results over a JSON command interface, with run.json, log and waves as output.

TCL / CLI

Scripts and shell

Build a flow interactively, then copy its commands from the transcript into a Tcl script.

MCP

AI agents

An agent discovers the same commands, then drives projects, simulation, waves, dissectors and coverage — and can start or stop runs itself.

project open h264.bitstorm.json
sim compile
sim run
sim assert-pass
coverage open
gui open review.session.json

The same operations are available through the command line and JSON. Projects and recordings can be prepared without a display, then opened in the GUI with waveforms, transcript and analysis settings ready.

Benchmarks

Simulated clock cycles per second on one workstation. Higher is faster.

Reference design	Bitstorm GPU engine Mcyc/s	Verilator 5, 1 thread Mcyc/s	Ratio
macpipe88-lane multiply-accumulate pipeline	53,422	21.1	2,532×
macfarm8 independent MAC pipelines, 322,517 gates	1,094	3.71	295×
holdpipeAXI-Stream pipeline	267	16.9	16×

Conditions

One workstation: Ryzen 9 5950X, 16 cores, and an RTX 5070 Ti. The GPU engine runs the GPU and one CPU core together; Verilator 5 runs on one thread, built with MSVC and -O3 --x-assign fast --x-initial fast --no-assert.
Engine rates use generated random inputs and outputs held in GPU memory: no testbench, no waveform output, best of three runs. The figures are two-state and cycle-based.
A behavioral testbench costs a few hundred nanoseconds per cycle and sets the rate of a GPU run that uses one. Streaming real stimulus from host memory adds PCIe transfers: 8 bytes of input per cycle over a 25 GB/s link caps a GPU run at about 3 billion cycles per second.
The GPU engine gains most on datapaths and video pipelines, and least on designs that are almost all control logic. holdpipe is the control-heavy case in this table.

Checked against other simulators

Check	Reference	Latest result
Automated test suite	Hand-computed traces and reference engines	228 pass, none fail
Engine parity	The CPU reference engines	Every net and output, every cycle
Golden simulation	Icarus Verilog on the same sources	Every engine matches Icarus
VHDL compliance	GHDL on VHDL-2008 Compliance-Tests	28 of 29
VHDL verification components	OSVVM test cases; UVVM demos	171 of 171; 3 of 3
Language suite	sv-tests, elaboration in event mode	855 accepted, 97% of 877

Acquire the company, or license it for a product you sell

Temporal Computing is available for acquisition; Bitstorm can also be licensed as part of a product you sell.

Diligence materials under NDA, and a remote evaluation machine to benchmark your own RTL and testbench.

We grant access by hand, so we will reply directly.

One product,both halves.