Hydra · RTL simulator

The world's fastest RTL simulator.

Verilator, ModelSim and Questa run a design on CPU cores. Hydra runs it on an NVIDIA GPU as well: thousands of GPU threads take the work that runs in parallel, and a fast CPU core takes the serial part — both on one simulation.

See the benchmarks

Designs that are mostly serial still run fast

Two engines under one command line, so a design or a testbench can use the engine that suits it.

GPU ENGINE

Parallel work on thousands of threads

Datapaths, video pipelines and other wide, parallel logic go to the GPU. The CPU core runs the serial part and the testbench, in the same simulation.

COMPILED CPU

Serial designs as compiled code

Designs that are mostly sequential run as compiled code on CPU cores, multithreaded, and gain from each thread you give them.

EVENT MODE

Sources, four-state, timed

Runs designs and testbenches from their sources with four-state values, delays, delta cycles and SDF timing — the semantics a UVM testbench expects.

What Hydra covers

Language support, verification features and the files your flow already produces.

LANGUAGES

SystemVerilog, Verilog, VHDL

SystemVerilog (IEEE 1800-2023, including Verilog 1364-2005), VHDL designs (IEEE 1076-2019), and the two mixed in one design.

VERIFICATION

UVM and constrained random

UVM 1.2 and 2020.3.1 in event mode, classes and constraints, functional coverage with merge and reports, SVA and PSL, plus SDF back-annotation.

INTEGRATION

DPI-C, VPI, VHPI, cocotb

DPI-C for C models; VPI and VHPI with cocotb in event mode; Xilinx's Vivado libraries in Verilog and VHDL with the 7 series SERDES; IEEE 1735 encrypted IP.

OUTPUT

FST or VCD, live during the run

Waves stream while the simulation runs and open directly in Bitstorm, where you can inspect them as they arrive.

CONTROL

A command line, JSON, pause and force

Drive runs from a script, another process over JSON, or an AI agent — directly, or through Bitstorm's MCP server. Pause mid-run, examine and force values, then resume.

PLATFORMS

Windows for the GPU, Linux too

GPU engine: Windows 10 or 11 with an NVIDIA Ampere or newer GPU. CPU engines and event mode also run on Linux (Ubuntu 22.04 or later).

From RTL to one simulation

Six steps, one command.

Compile

SystemVerilog, Verilog, VHDL and testbenches.

Analyze

Find the parallel and the serial work.

Partition

Split work between GPU threads and CPU cores.

Schedule

Order GPU and CPU work to run together.

Execute

Hybrid CPU and GPU engines, one simulation.

Results

run.json, log, and FST or VCD waves.

Agent-ready

Hydra speaks JSON, so a script and an AI agent drive it the same way: one request per step, results in a file.

AGENT-READY

Every step is a request

Compile, run, pause, examine, force a value and collect results over Hydra's JSON command interface — no GUI, no human in the loop.

VIA BITSTORM

Agents reach Hydra today

Bitstorm calls Hydra as a process. Through Bitstorm's MCP server an agent sets up the project, runs the simulation and inspects waves and coverage.

EVIDENCE

Results an agent can report

run.json, the log, and FST or VCD waves — so the agent reports which signal failed at which cycle, not just an exit code.

# the loop an agent runs against Hydra
compile   design + testbench, on the engine that fits
run       CPU, GPU or event mode
status    pause, examine or force a value mid-run
results   run.json, log, FST or VCD waves

A native MCP server for Hydra is in development, so an agent will be able to drive the simulator without Bitstorm. Until then the JSON interface, and Bitstorm's MCP, cover the same ground.

Benchmarks

Simulated clock cycles per second on one workstation. Higher is faster.

Reference design	Hydra, GPU engine Mcyc/s	Verilator 5, 1 thread Mcyc/s	Hydra / Verilator
macpipe88-lane multiply-accumulate pipeline	53,422	21.1	2,532×
macfarm8 independent MAC pipelines, 322,517 gates	1,094	3.71	295×
holdpipeAXI-Stream pipeline	267	16.9	16×

Conditions

One workstation: Ryzen 9 5950X, 16 cores, and an RTX 5070 Ti. Hydra's GPU engine runs the GPU and one CPU core together; Verilator 5 runs on one thread, built with MSVC and -O3 --x-assign fast --x-initial fast --no-assert.
Engine rates use generated random inputs and outputs held in GPU memory: no testbench, no waveform output, best of three runs. The figures are two-state and cycle-based.
A behavioral testbench costs a few hundred nanoseconds per cycle and sets the rate of a GPU run that uses one. Streaming real stimulus from host memory adds PCIe transfers: 8 bytes of input per cycle over a 25 GB/s link caps a GPU run at about 3 billion cycles per second.
The GPU engine gains most on datapaths and video pipelines, and least on designs that are almost all control logic. holdpipe is the control-heavy case in this table.

Checked against other simulators

Open test suites and golden references, run beside Hydra on the same sources.

Check	Reference	Latest result
Automated test suite	Hand-computed traces and reference engines	228 pass, none fail
Engine parity	The CPU reference engines	Every net and output, every cycle
Golden simulation	Icarus Verilog on the same sources	Every engine matches Icarus
VHDL compliance	GHDL on VHDL-2008 Compliance-Tests	28 of 29
VHDL verification components	OSVVM test cases; UVVM demos	171 of 171; 3 of 3
Language suite	sv-tests, elaboration in event mode	855 accepted, 97% of 877

Waves from a validation run are compared value for value against the CPU engine, and Bitstorm imports the same FST file.

Hydra is available for acquisition or non-exclusive license. Diligence materials under NDA, and a remote evaluation machine to benchmark your own RTL and testbench.

We grant access by hand, so we will reply directly.